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PRELIMINARY
APRIL 2006
XRK697H73
REV. P1.0.0
1:12 LVCMOS PLL CLOCK GENERATOR
GENERAL DESCRIPTION
The XRK697H73 is a PLL based LVCMOS Clock Generator targeted for high performance and low skew clock distribution applications. The XRK697H73 can select between one of three reference inputs and provides 14 LVCMOS outputs -12 outputs (3 banks of 4) for clock distribution, 1 for feedback and 1 for synchronization. The XRK697H73 is a highly flexible device. It has 3 selectable inputs, (one differential and two single-ended inputs) to support system clock redundancy. Up to three different clock frequencys can be generated and outputted on the three output banks. Switching the internal reference clock is controlled by the control input, CLK_SEL. The XRK697H73 uses PLL technology to frequency lock its outputs to the input reference clock. The divider in the feedback path will determine the frequency of the VCO. Each of the separate output banks can individually divide down the VCO output frequency. This allows the XRK697H73 to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. The outputs of the XRK697H73 can individually be immobilized, in the low state, by use of the clock stop feature. All outputs except QC0 and QFB can be immobilized through a 2 pin serial interface. Global output disabling and reset can be achieved the control input MR/OE. The XRK697H73 also has a QSYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period of the
faster clock prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer
multiples of one another.
The XRK697H73 has an output frequency range of 8.33MHz to 240MHz and an input frequency range of 5MHz to 120MHz.
FEATURES
* Fully Integrated PLL * Selectable Differential PECL or LVCMOS inputs for
reference clock source
* 14 LVCMOS outputs

3 banks with 4 outputs each. Frequencies can be individually controlled by bank 1 dedicated feedback with frequency control 1 Sync
* VCO Range 200MHz to 480MHz * Output freq. range: 8.33MHz to 240MHz * Max Output Skew of 250ps * Cycle-to-cycle jitter: 150ps (typ)
APPLICATIONS
* System Clock generator * Zero Delay Buffer
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER XRK697H73CR XRK697H73IR PACKAGE TYPE 52-LEAD LQFP 52-LEAD LQFP OPERATING TEMPERATURE RANGE 0C to +70C -40C to +85C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRK697H73
1:12 LVCMOS PLL CLOCK GENERATOR
PRELIMINARY
REV. P1.0.0
FIGURE 1. BLOCK DIAGRAM OF THE XRK697H73
STOP PECL PECL XTAL
QA0
0 VDD 1 0 Ref VCO
/2
DIVIDER SELECT 0 0 1 BANK A BANK B BANK C
/4, /6, /8, /12 /4, /6, /8, /10
STOP
QA1
CLK0
STOP
QA2
CLK1 CLK_SEL
1
PLL
200-480MHz VDD
1
/2, /4, /6, /8
/4, /6, /8, /10, /12, /16, /20
STOP
QA3
FB
STOP
QB0
Sync Pulse REF_SEL FB_IN VCO_SEL PLL_EN
STOP
QB1
FB
STOP QB2
STOP
QB3
VDD
QC0 FSEL_A[1:0] FSEL_B[1:0] FSEL_C[1:0] FSEL_FB[2:0] 2 2 2 3 STOP QC1
0
STOP
QC2
1 VDD
INV_CLK
STOP
QC3
POWER-ON RESET
QFB
STOP STOP_DATA STOP_CLK MR/OE
QSYNC
SERIAL INTERFACE
12
FIGURE 2. PIN OUT OF THE XRK697H73
VCO_SEL FSEL_A0 FSEL_A1 FSEL_B0 41 FSEL_B1 40 39 38 37 36 35 34
GND
GND
VDD
VDD 45
QA0
QA1
QA2
GND ___ MR/OE STOP_CLK STOP_DATA FSEL_FB2 PLL_EN REF_SEL CLK_SEL CLK0 CLK1 PECL PECL VDD_PLL
52 1 2 3 4 5 6 7 8 9 10 11 12 13 14
51
50
49
48
47
46
44
QA3
43
42
GND QB0 VDD QB1 GND QB2 VDD QB3 FB_IN GND QFB VDD FSEL_FB0
XRK697H73
33 32 31 30 29 28
15
16
17
18
19
20
21
22
23
24
25
27 26
INV_CLK
QC3
QC2
QC1
FSEL_C1
FSEL_C0
GND
QC0
GND
VDD
VDD
QSYNC
2
FSEL_FB1
PRELIMINARY
REV. P1.0.0
XRK697H73
1:12 LVCMOS PLL CLOCK GENERATOR
PIN DESCRIPTIONS
PIN # 1,15, 24, 30, 35, 39, 47, 51 2 3 4 5, 26, 27 6 7 8 9 10 11 12 13 14 17, 22, 28, 33, 37, 45, 49 19,20 25 29 31 32, 34, 36, 38 40, 41 42, 43 44, 46, 48, 50 52 NAME GND MR/OE STOP_CLK STOP_DATA FSEL_FB[2:0] PLL_EN REF_SEL CLK_SEL CLK0 CLK1 PECL PECL VDD_PLL INV_CLK VDD FSEL_C[1:0] QSYNC QFB FB_IN QB[3:0] FSEL_B[1:0] FSEL_A[1:0] QA[3:0] VCO_SEL TYPE POWER INPUT* INPUT* INPUT* INPUT* INPUT* INPUT* INPUT* INPUT* INPUT* INPUT POWER INPUT* POWER INPUT* OUTPUT OUTPUT INPUT* OUTPUT INPUT* INPUT* OUTPUT INPUT* Power supply ground Master reset and output enable. High = output enabled, Low = device reset & outputs tri-stated Clock input for serial control. Data input for serial control Select inputs for control of feedback divide value. PLL bypass. High = PLL, Low = PLL bypass Xtal or CLK select. High = Xtal input selected, Low = CLK0 or CLK1 selected CLK0 or CLK1 Select. High = CLK1 selected, Low= CLK0 selected PLL Reference Clock Inputs Diffferential LVPECL Clock Input Analog supply for PLL Invert clock select for QC3 & QC2. High = invert, Low = normal operation Power supply for outputs. Bank C divide select pins. Synchronization output for Bank A and Bank C. Feedback clock output Feedback input Clock outputs (Bank B) Bank B divide select pins. Bank A divide select pins. Clock outputs (Bank A) VCO select. High = VCO/1, Low = VCO/2. DESCRIPTION
* 25K pull-up resistor
3
XRK697H73
1:12 LVCMOS PLL CLOCK GENERATOR 1.0 ELECTRICAL SPECIFICATIONS TABLE 1: GENERAL SPECIFICATIONS
SYMBOL VTT ESDMM ESDHBM LU CIN CHARACTERISTICS Output Termination Voltage ESD Protection (Machine model) ESD Protection (Human body model) Latch-up Immunity Input capacitance
PRELIMINARY
REV. P1.0.0
CONDITION
MIN
TYP
MAX
UNIT
VDD/2 200 2000 200 per input 4
V V V mA pf
TABLE 2: ABSOLUTE MAXIMUM RATINGS
SYMBOL VDD VIN VOUT IIN IOUT TS CHARACTERISTICS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65
CONDITION MIN TYP MAX UNIT
-0.3 -0.3 -0.3
3.9 VDD + 0.3 VDD + 0.3 +/-20 +/-50 125
V V V mA mA C
TABLE 3: DC CHARACTERISTICS (VDD = 3.3V +/- 5%)
SYMBOL VDD_PLL VIH VIL VPP VCMR VOH VOL ZOUT IPU IDD_PLL IDDQ CHARACTERISTICS PLL Supply Voltage Input High Voltage Input Low Voltage Peak to Peak Input Voltage PECL and PECL Common Mode Range PECL and PECL Output High Voltage Output Low Voltage LVPECL LVPECL IOH = -24mA IOL = 24mA IOL = 12mA 8-11 VIN = GND or VDD @ VDD_PLL Pin -100 8 200 13.5 35 250 1.0 2.4 0.55 0.30 VDD - 0.6
CONDITION MIN TYP MAX UNIT
3.0 2.0
VDD VDD+ 0.3 0.8
V V V mV V V V A mA mA
Output Impedance Input Current PLL Supply Current Quiescent Supply Current
4
PRELIMINARY
REV. P1.0.0
XRK697H73
1:12 LVCMOS PLL CLOCK GENERATOR
TABLE 4: AC CHARACTERISTICS (VDD = 3.3V +/- 5%)
SYMBOL fREF CHARACTERISTICS Input reference frequencya
CONDITION MIN TYP MAX UNIT
/4 feedback /6 feedback /8 feedback /10 feedback /12 feedback /16 feedback /20 feedback /24 feedback /32 feedback /40 feedback PLL bypass mode
50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 6.25 5.00
120 80.0 60.0 48.0 40.0 30.0 24.0 20.0 15.0 12.0 250 480 240.0 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 20.0
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz mV V ns
fVCO fMAX
VCO frequency range Output frequencya /2 output /4 output /6 output /8 output /10 output /12 output /16 output /20 output /24 output
200 100.0 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33
fSTOP_CLK VPP VCMR tPW ItR, ItF t()
Serial interface frequency Peak to Peak Input Voltage PECL and PECL Common Mode Range PECL and PECL CLKx pulse width Input CLKx Rise/Fall time 0.8V to 2.0V -3 -4 -166 LVPECL LVPECL 400 1.2 2.0
1000 VDD - 0.9
1 +3 +4 +166 100 100 100 250 (T/2)-200 T/2 (T/2)+200 1.0
ns ps ps ps ps ps ps ns
Propagation Delay (static 6.25MHz < fREF < 65.0MHz phase offset) CLKx to FB_INb 65.0MHz < fREF < 125MHz fREF = 50MHz & FB = /8
tSK(O)
Output to output skew
Bank A (QAx to QAy) Bank B (QBx to QBy) Bank C (QCx to QCy) all outputs (QXy to QWz)c
DC OtR, OtF
Output duty cycled Output Rise/Fall time 0.55 to 2.4V
0.1
5
XRK697H73
1:12 LVCMOS PLL CLOCK GENERATOR
PRELIMINARY
REV. P1.0.0
TABLE 5: AC CHARACTERISTICS (CON'T) (VDD = 3.3V +/- 5%)
SYMBOL tPLZ, tPHZ tPZL, tPZH tJIT(CC) tJIT(PER) tJIT(O) CHARACTERISTICS Output Disable Time Output Enable Time Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter RMS (1 ) VCO = 400MHz All outputs in same divider config. All outputs in same divider config. /4 feedback /6 feedback /8 feedback /10 feedback /12 feedback /16 feedback /20 feedback /24 feedback /32 feedback /40 feedback /4 feedback /6 feedback /8 feedback /10 feedback /12 feedback /16 feedback /20 feedback /24 feedback /32 feedback /40 feedback 1.20-3.5 0.70-2.50 0.50-1.80 0.45-1.20 0.30-1.00 0.25-0.70 0.20-0.55 0.17-0.40 0.12-0.30 0.11-0.28 10 150
CONDITION MIN TYP MAX UNIT
8 8 200 150 11 86 13 88 16 19 21 22 27 30
ns ns ps ps ps ps ps ps ps ps ps ps ps ps MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ms
BW
PLL closed loop bandwidth
tLOCK NOTES:
PLL Lock Time
a. PLL locked, except when configured in bypass mode. b. t(O)[s] = t(O)[] / (fref x 360) c. Not including Qsync output d. T is the output period.
FIGURE 3. TEST LOAD
Transmission Line Z = 50 50
VTT
6
PRELIMINARY
REV. P1.0.0
XRK697H73
1:12 LVCMOS PLL CLOCK GENERATOR
2.0 CONFIGURATION TABLES TABLE 6: FUNCTION CONTROLS
CONTROL PIN MR/OE PLL_EN LOGIC 0 Resets the output divide circuitry and serial interface, tri-states all outputs PLL bypass mode enabled. This is a test mode in which the reference clock is provided to the output dividers in place of the VCO. CLKx selected as ref source to PLL CLK0 selected QC2 & QC3 are in phase with QC1 & QC4 LOGIC 1 Enables all outputs - normal operation PLL enabled - normal operation
REF_SEL CLK_SEL INV_CLK
PECL & PECL inputs selected as ref source to PLL CLK1 selected QC2 & QC3 are 180out of phase with QC1 & QC4 no divide of VCO
VCO_SEL
VCO / 2
TABLE 7: BANK OUTPUT DIVIDER CONTROLS
INPUT FSEL_A1 0 0 1 1 FSEL_A0 0 1 0 1 OUTPUT QA /4 /6 /8 /12 INPUT FSEL_B1 0 0 1 1 FSEL_B0 0 1 0 1 OUTPUT QB /4 /6 /8 /10 INPUT FSEL_C1 0 0 1 1 FSEL_C0 0 1 0 1 OUTPUT QC /2 /4 /6 /8
TABLE 8: FEEDBACK DIVIDER CONTROL
FSEL_FB2 0 0 0 0 1 1 1 1 FSEL_FB1 0 0 1 1 0 0 1 1 FSEL_FB0 0 1 0 1 0 1 0 1 QFB /4 /6 /8 /10 /8 /12 /16 /20
7
XRK697H73
1:12 LVCMOS PLL CLOCK GENERATOR 3.0 QSYNC TIMING FIGURE 4. QSYNC TIMING DIAGRAM
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2
PRELIMINARY
REV. P1.0.0
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
fVCO 1:1 Mode QA QC QSYNC 2:1 Mode QA QC QSYNC 3:1 Mode QC(/2) QA(/6) QSYNC 3:2 Mode QA(/4) QC(/6) QSYNC 4:1 Mode QC(/2) QA(/8) QSYNC 4:3 Mode QA(/6) QC(/8) QSYNC 6:1 Mode QA(/12) QC(/2) QSYNC
XRK697H73 INDIVIDUAL OUTPUT DISABLE (STOP CLOCK) CIRCUITRY The user can write to the serial input register through the STOP_DATA input by supplying a logic '0' start bit followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the free-running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the XRK697H73 can sample each STOP_DATA bit with the rising edge of the free-running STOP_CLK signal. A logic "0" to any stop bit location will disable the corresponding device output while a logic "1" will enable. All outputs are by default, enabled. FIGURE 5. STOP CLOCK CIRCUIT PROGRAMMING
STOP_CLK
STOP_DATA
START
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC1
QC2
QC3
QSYNC
8
PRELIMINARY
REV. P1.0.0
XRK697H73
1:12 LVCMOS PLL CLOCK GENERATOR
FIGURE 6. OUTPUT-TO-OUTPUT SKEW tSK(O)
VCC VCC/2 GND VCC VCC/2 GND tSK(O)
The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device.
FIGURE 7. PROPOGATION DELAY (t(O), STATIC PHASE OFFSET) TEST REFERENCE
VCC CCLKx VCC/2 GND VCC FB_IN VCC/2 GND t(O)
FIGURE 8. OUTPUT DUTY CYCLE (DC)
VCC VCC/2 tp T0 DC=tP/T0 x 100%
The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
GND
FIGURE 9. I/O JITTER
CCLKx
FB_IN TJIT(I/O) = |T0-T1mean |
The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles
9
XRK697H73
1:12 LVCMOS PLL CLOCK GENERATOR
PRELIMINARY
REV. P1.0.0
FIGURE 10. CYCLE-TO-CYCLE JITTER
TN
TN+1
TJIT(CC)= |TN-TN+1 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
FIGURE 11. PERIOD JITTER
T0
TJIT(Per)= |TN-1/f0 |
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
FIGURE 12. OUTPUT TRANSITION TIME TEST REFERENCE VCC=3.3V 2.4 0.55 OtF OtR
10
PRELIMINARY
REV. P1.0.0
XRK697H73
1:12 LVCMOS PLL CLOCK GENERATOR
PACKAGE DIMENSIONS
E
52 LEAD LOW-PROFILE QUAD FLAT PACK (10 mm x 10 mm X 1.4 mm LQFP, 1.0 mm Form)
Rev. 1.00
Note: The control dimension is in millimeters. INCHES MIN MAX 0.055 0.063 0.002 0.006 0.053 0.057 0.010 0.014 0.004 0.009 0.465 0.480 0.390 0.398 0.0256 BSC 0.029 0.041 0 7 MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.25 0.35 0.11 0.23 11.80 12.20 9.90 10.10 0.65 BSC 0.73 1.03 0 7
SYMBOL A A1 A2 B C D D1 e L
11
XRK697H73
1:12 LVCMOS PLL CLOCK GENERATOR REVISION HISTORY
REVISION # P1.0.0 DATE April 7, 2006 Initial release.
PRELIMINARY
REV. P1.0.0
DESCRIPTION
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2006 EXAR Corporation Datasheet April 2006. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
12

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